We are looking for a senior engineer to be part of the mixed-signal design team building next generation NVLINK. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

We are actively looking for Physical design Engineers with RTL2GDS experience to implement complex high performance and low power SOC’s.

What you'll be doing:

• Responsible to Floor Planning and Place and route (P&R) of High-performance chip partitions.

• Integration on Analog IO’s and macros.

• Work on power grid planning, Clock tree Synthesis (CTS) and timing closure.

• Multi mode and multi corner timing closure, RC extraction, Cross talk, IR drop and EM analysis.

• Work with the Front-end teams to update and create timing constraints.

• Debugging timing violations and rolling in functional, Timing ECO’s and netlist formal verification.

• Physical verification including ERC, DRC, LVS etc.

What we need to see:

• BSEE / MSEE or equivalent experience.

• Minimum 5+ years of experience in VLSI physical design implementation on 16nm, 7nm, 5nm or 3nm technology.

• Able to assist in design flow development and debugging.

• Already a validated strong power user of P&R, Timing analysis, Physical Verification and IR Drop Analysis CAD tools from Synopsys (ICC2/DC/PT/STAR/ICV), Cadence (Genus/Innovus/Tempus) and other major EDA companies.

• To be successful you should possess strong analytical and debugging skills.

• Proficiency using Python, Perl, Tcl, Make scripting is desired.