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Senior SOC Infrastructure and Methodology Design Engineer

Excelero Storage

Excelero Storage

Other Engineering, Design
hsinchu, east district, hsinchu city, taiwan
Posted on Oct 27, 2025

The NVIDIA SOC System-ASIC team is looking for a Infrastructure and Methodology engineer with an interest in developing new tools and optimizing existing design flow & process to improve design work efficiency and quality. The ideal candidate for this position needs to have strong programming skills, communication skills, and broad ASIC design/verification knowledge.

SOC System-ASIC team focuses on developing some System/Top-level related control and measurement units and features, like: Fuse/Strap, Floorsweep, Reset, ISM and Sysctrl. Those units are important functions in all NVIDIA products. You will have opportunities to understand the details of those functions and the detailed NVIDIA working flow & process about how to deliver those functions successfully. The design of those functions becomes more and more complex therefore to fully verify those implementations and ensure bug-free within the tight schedule becomes more and more challenging. So the Infrastructure and Methodology work are more and more important. Your mission is cooperating with talents inside SOC System-ASIC team and NVIDIA infrastructure team to develop some innovative and groundbreaking tools, working flow & processes to improve whole team design efficiency and quality.

What you’ll be doing:

  • Be involved in some design work for the IPs and features owned by System-ASIC team

  • Brainstorm with IP design owners to figure out suffering points or discuss infra-related improvement ideas. Settle down the specific requirement and choose the suitable methodology to develop infrastructure flow/tool

  • Responsible for Reset methodology work, include: utilize in-house or industry commercial tool and flow to guarantee reset design quality, develop new tool or flow to improve reset design quality and efficiency

What we need to see:

  • MS in EE/CE/CS

  • 2+ years of design or design methodology experience

  • Strong coding skill for Python, Perl, TCL, JavaScript etc.

  • Understand ASIC design/verification flow and have experience for CDC/RDC/Synthesis/Timing closure

  • Fluent English (both written and spoken) and excellent communication skills to interface with many groups and build consensus

Ways to stand out from the crowd:

  • Good team work spirit, easy to cooperate with team members

  • Has Web system, Database knowledge is a plus

  • Knowledge on deep-learning experience is a plus